The present invention relates to an encoder, decoder, and transmission system, and is preferably adapted to, for example, an encoder that encodes data items into successive first and second encoded data items, a decoder, and a transmission system.
In recent years, various transmission systems have been highly requested to cope with high-speed transmission. A high-speed serial interface that enables faster data transmission than parallel data transmission is widely used.
For example, display devices including a liquid crystal panel have the frame frequency progressively increased for the purpose of realizing high definition, employing multiple colors, displaying a motion picture, and achieving three-dimensional display. A data volume to be transferred from a timing controller to a display driver integrated circuit (IC) is increasing year by year, and an interface to be employed in the timing controller and display driver IC alike is requested to operate at a high speed. Many proposals have been made of a clock embedded serial data transmission method for serially transmitting clock embedded data.
In general, in clock embedded serial data transmission, a clock reproduction method in which clock components are extracted from a signal received by a receiving unit in order to reproduce a clock is adopted. In transmission according to the clock reproduction method, when signals with the same level are successively received, the clock components cannot be highly precisely reproduced. This makes it necessary to adopt an encoding method according to which the signals with the same level do not successively appear. Specifically, assuming that a digital signal including bits which represent 1 or 0 when driven to a high level or a low level is encoded into encoded data, a run of bits with the same logic level should not be produced.
As an encoding method that prevents production of successive signals with the same level, an mBnB encoding method of encoding a signal into an mBnB code is known. This method is such that a signal of m bits long (where m denotes a natural number) is encoded into a signal of n bits long (where n denotes a natural number and is larger than m) on the basis of a certain conversion table, and then transmitted. The method is intended to suppress a run of bits with the same logic level among the n bits resulting from the encoding. The 4B5B encoding method, 8B10B encoding method, or the like is widely adopted. For example, the 4B5B encoding method is adopted by the IEEE 802.3u that is the standard for Ethernet (registered trade mark).
As related arts of performing mBnB encoding, the arts described in, for example, patent documents 1 and 2 (Japanese Patent Application Laid-Open Nos. 2001-69181 and 2000-224242) are known.
FIG. 18 shows an existing transmission system described in the patent document 1. In the patent document 1, mBnB block encoding is performed for ready identification of a clock during data transfer, and non-return-to-zero-inverted (NRZx) conversion is further performed in order to transfer the resultant data. Thus, repetition of a certain-level signal is suppressed.
Specifically, in the existing transmission system shown in FIG. 18, a 4B5B converter 901 in a transmission unit converts transmission data of four bits long into five bits in conformity with one-to-one correspondence encoding rules. A parallel-serial converter 902 converts parallel data, which has been converted from four bits to five bits, into serial data. Further, a NRZ1 converter 903 performs non-return-to-zero-inverted conversion or non-return-to-zero change-on-ones conversion on the serial data.
In the NRZ1 converter 903, when an input value is 0, the next output does not change. When the input value is 1, the next output is an inverse of the preceding bit. Therefore, in case a run of bits with the same level is inputted, the maximum number of bits comes to the sum of the number of successive 0 bits, which are inputted to the NRZ1 converter 903, and one bit. When the one-to-one correspondence encoding rules are applied, the longest run of 0s is two bits long. Therefore, the longest run of certain-level bits is three bits long.
In the existing transmission system shown in FIG. 18, in a receiving unit, a clock extraction circuit 908 reproduces a clock from receiving data sent from the transmission unit. An NRZ1 inverter 905 uses the reproduced clock to perform inversion so as to obtain an exclusive OR of current receiving data and one-clock preceding receiving data. A serial-parallel converter 906 converts the result of the inversion into parallel data of five bits long. A 4B5B inverter 907 inverts 5-bit data, which results from serial-parallel conversion, in conformity with the one-to-one correspondence encoding rules employed on the transmission side, and reproduces transmission data of four bits long.
FIG. 19 shows an existing transmitter described in the patent document 2. According to the patent document 2, in serial data transfer, a synchronizing (sync) character for use in alignment of bits is embedded in data in order to eliminate the transfer period of the sync character and reduce a transfer rate. For embedding the sync character, when identical data is repeated twice, the second data is used as the sync character. Thus, the alignment of bits and outputting of identical data are achieved.
Specifically, in the transmitter shown in FIG. 19, a timing production circuit 911 produces a series of clocks having a predetermined clock cycle. A data latch 912 is coupled to the timing production circuit 911. Every time the data latch 912 receives one of the series of clocks, the data latch 912 latches input parallel data of m bits long as latch data that is parallel data of m bits long. An mBnB conversion circuit 913 is coupled to the data latch 912, and converts the parallel latch data of m bits long into parallel conversion data of n bits long. A sync character production circuit 914 produces a sync character that is parallel data of n bits long which is inconsistent with the parallel conversion data of n bits long.
A latch data comparison circuit 917 is coupled to each of the timing production circuit 911 and data latch 912. Every time the latch data comparison circuit 917 receives one of a series of clocks as a current clock, the latch data comparison circuit 917 compares the latch data, which is parallel data of m bits long and which the data latch 912 has latched as current latch data on receipt of the current clock, with latch data which is parallel data of m bits long and which the data latch 912 has latched as preceding latch data on receipt of a preceding clock that is a clock preceding the current clock. While the current latch data is consistent with the preceding latch data, the latch data comparison circuit 917 outputs a consistency signal.
A selector 915 is coupled to each of the mBnB conversion circuit 913, sync character production circuit 914, and latch data comparison circuit 917, and receives the conversion data, which is parallel data of n bits long, and the sync character. When the selector 915 does not receive the consistency signal, the selector 915 selectively outputs the conversion data, which is parallel data of n bits long, as output data that is parallel data of n bits long. When the selector 915 receives the consistency signal, the selector 915 selectively outputs the sync character, which is parallel data of n bits long, as output data that is parallel data of n bits long. A parallel-serial conversion circuit 916 is coupled to the selector 915, and converts the parallel data of n bits long into serial data.